In a field of electronics, much higher density and greater efficiency of device mounting are required. Then, attention is attracted to a bonding technique termed the three-dimensional mounting, for bonding a substrate on which a semiconductor integrated circuit and an electrical wiring have been already formed to another similar substrate. By adopting this method, various three-dimensional mountings from the chip level to the wafer level, such as COC (Chip On Chip), COW (Chip On Wafer), and WOW (Wafer On Wafer), can be achieved, and when this mounting technique is applied to a wafer having a larger area, in the three-dimensional mountings such as WOW (Wafer On Wafer) and WLP (Wafer-Level Packaging), it becomes possible to layer electrical elements and/or circuits on a wafer in a vertical direction. Further, it is possible to bond an electric circuit or an electrical wiring which is formed on one substrate to the corresponding electric circuit or the corresponding electrical wiring which is formed on the other substrate in a wafer surface direction at a time. Therefore, by this technique, both the three-dimensional mounting of the semiconductor integrated circuit and greater efficiency of the manufacturing method can be achieved at the same time.
In respective surfaces of the wafers, provided are metal regions each of which is electrically connected or to be electrically connected to the above electric circuit or the like, and by establishing an electric connection between these metal regions in the bonding process, an electric connection is established between the wafers. In the bonding process, generally, first, alignment of the wafers to be bonded is performed between the corresponding metal regions in the wafer surface direction. Next, the wafers are made closer to each other so that the metal regions can come into contact with each other, and a force is exerted in a direction vertical to the wafer surface. Then, by heating the wafers to a relatively high temperature, diffusion of atoms is caused between the metal regions, to thereby establish the electric connection.
Incidentally, the bonding under high temperature is not suitable for bonding between thin wafers or between different materials having different coefficients of thermal expansion. Then, proposed is a technique in which a surface activation treatment is performed on the metal regions by irradiating the bonding surfaces with an ion beam or a fast atom beam and then the respective bonding surfaces of the wafers are adhered to each other so that the metal regions can come into contact with each other and heated, to thereby bond the wafers at relatively low temperature.
On the other hand, the surface activated bonding technique is not suitable for bonding of a member of ionic crystal such as silicon oxide, silicon nitride, quartz, or the like. Then, Japanese Patent Application Laid-Open No. 2004-337927 (Document 1) discloses a technique in which a metal thin film is formed on each of the bonding surfaces of the substrates by irradiating the bonding surfaces with a metal ion beam or a metal neutral atom beam together with an inert gas ion beam or an inert gas neutral atom beam and bonding is thereby performed by surface activation even on the member of ionic crystal. Irradiation with the metal ion beam or the metal neutral atom beam is achieved by using a beam source whose grid is formed of a metal.
Japanese Patent Application Laid-Open No. 2007-324195 (Document 2) discloses a technique in which a vacuum chamber and a stage supporting the substrate are formed of stainless steel and charged particles from an ion gun collide against these members, to thereby cause a plurality of types of metals to be contained into the activated surface in the surface activation of the bonding surface. Japanese Patent Application Laid-Open No. 2008-62267 (Document 3) discloses an arrangement of the targets in order to efficiently cause a plurality of types of metals to be contained into the activated surface.
Further, in WO 2012/105474 (Document 4), disclosed is a technique in which silicon thin films are formed on the respective bonding surfaces of the substrates by sputtering the silicon target and the substrates are bonded by using the silicon thin films.
As disclosed in Documents 1 to 4, various bonding methods using surface activation are proposed.